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We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10&#x00D7;12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 &#x03BC;m<sup>2</sup> per cell, and is at least one order of magnitude more dense than the reported prior implementations of nonvolatile analog memories. The demonstrated vector-by-vector multiplier, using gate coupling to additional periphery cells, has ~2% precision, limited by the aggregate effect of cell noise, retention, mismatch, process variations, tuning precision, and capacitive crosstalk. A differential version of the multiplier has allowed us to demonstrate sub-3% temperature drift of the output signal in the range between 25 &#x00B0;C and 85 &#x00B0;C.

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells