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Shrinking process technology and rising memory densities have made memories increasingly vulnerable to errors. Accordingly, DRAM vendors have introduced <italic>On-die Error Correction Code (O-ECC)</italic> to protect data against the growing number of errors. Current O-ECC provides weak <italic>Single Error Correction (SEC)</italic>, but future memories will require stronger protection as error rates rise. This paper proposes a novel ECC, called <italic>Single Error Correction&#x2013;Byte-Aligned Double Adjacent Error Correction (SEC-BADAEC)</italic>, and its construction algorithm to improve memory reliability. SEC-BADAEC requires the same redundancy as SEC O-ECC, but it can also correct some frequent 2-bit error patterns. Our evaluation shows SEC-BADAEC can improve memory reliability by 23.5&#x0025; and system-level reliability by 29.8&#x0025; with negligible overheads.

SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection