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As laptops get thinner and thinner, the electronic packages that go into these devices must shrink along the <inline-formula> <tex-math notation="LaTeX">$z$ </tex-math></inline-formula>-dimension as well. High warpage in these ultra-thin packages is the result of mismatch of coefficients of thermal expansion (CTE) between the silicon die (CTE &#x003D; 2.6 ppm/C) and the organic substrate (CTE &#x003D; 12 to 16 ppm/C) and the reduced flexural rigidity due to reduced thickness. This can result in decreased yield during assembly onto the board. Through the selection of low CTE materials and the implementation of stiffeners, warpage can be decreased. This work aims to optimize the metal density in the substrate to achieve low warpage. An inverse design framework is implemented to optimize the surface warpage profiles of the package using heuristic global optimization method viz. Particle Swarm Optimization (PSO) and Cross Entropy (CE) on a surrogate model that is built using finite element analysis (FEA), tensor train decomposition (TTD) and artificial neural networks (ANN). Results demonstrate that using this framework can result in more than 10&#x0025; reduction in warpage by implementing up to 50&#x0025; decrease in metal density on the ground and power layers in the substrate. Further analysis is required to determine the impact of these changes to signal and power integrity. In future, the framework can be implemented to realize even thinner packages without compromising on their functionality.

Global Optimization of Surface Warpage for Inverse Design of Ultra-Thin Electronic Packages Using Tensor Train Decomposition