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In this paper, a kind of four-layer stack capacitor is proposed, which has realized the compatibility with the conventional standard <inline-formula> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The effective capacitance per area of the proposed stack capacitor is about three times larger than that of the mono-layer MOS capacitor. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the presented four-layer stack capacitor has been also established with considering the fringe effect. The results show that the root mean square error of the proposed SPICE model is less than 2&#x0025;. The model has been applied in the simulation design of the infrared focal plane array readout circuit (IRFPA ROIC) successfully. Based on the improved <inline-formula> <tex-math notation="LaTeX">$0.5~\mu \text{m}$ </tex-math></inline-formula> CMOS process with four-layer stack capacitor, an IRFPA ROIC with <inline-formula> <tex-math notation="LaTeX">$640\times 512$ </tex-math></inline-formula> array has been implemented and the dynamic range is improved from 73db to 78dB.

Novel Multiple-Layer Stack Capacitor and Its Application in the IRPFA Readout Circuit