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In this study, we propose an analog CMOS integrate-and-fire (I &#x0026; F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I &#x0026; F neuron circuit, the basic I &#x0026; F and synaptic off-current blocking operations of the proposed I &#x0026; F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I &#x0026; F neuron circuits. The simulation and analysis results demonstrate the robustness of the I &#x0026; F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices.

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation