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In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high ION( 1.231&#x00D7;10-4 A/&#x03BC;m) and ION/IOFF ratio ( 2.52&#x00D7;105) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having ION (1&#x00D7;10-7A/&#x03BC;m) and ION/IOFF ratio ( 1&#x00D7;102). It has been observed that there is more than 100 times improvement in cutoff frequency ( fT), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency ( fmax) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98% and 33.33% in switching ON and OFF delays respectively in the proposed device-based inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues.

2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications