English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Near-threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula>) operation is an effective method for lowering energy consumption. However, it increases the impact of <inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula> variation significantly, which makes it difficult for previously proposed static random access memory (SRAM) bitcells to achieve high read stability and write ability yields. To achieve these in the near-<inline-formula> <tex-math notation="LaTeX">$V_{th}$ </tex-math></inline-formula> region, a differential 7T SRAM bitcell is proposed in which an additional row-based control signal and an nMOS transistor between the pull-up and pull-down transistors is adopted on one side of the cross-coupled inverter. In addition, the proposed SRAM bitcell can use a bit-interleaved structure without the half-select issue. Compared to differential 10T and 12T SRAM, the proposed differential 7T SRAM achieves 5&#x0025; and 6&#x0025; higher SRAM operating frequency and 70&#x0025; and 23&#x0025; lower operation energy consumption with a 33&#x0025; and 49&#x0025; smaller bitcell area, respectively.

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation