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This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to realize a low-power/low-noise loop filter that is robust to temperature variation. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented to overcome the challenge of finding correct digital bit weights for NS SAR ADCs. Fabricated in 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, the prototype ADC demonstrates a peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB and a dynamic range of 74 dB with a signal bandwidth of 625 kHz. Over 80-degree of the temperature range, the ADC exhibits only 2 dB drop in SNDR thanks to the temperature-compensated dynamic amplifier. With a total power consumption of <inline-formula> <tex-math notation="LaTeX">$130~\mu \text{W}$ </tex-math></inline-formula>, the ADC achieves Walden Figure-of-Merit (FoM) of FoM<inline-formula> <tex-math notation="LaTeX">$_{\text {W}}= 34.4$ </tex-math></inline-formula> fJ and Schreier FoM of FoM<inline-formula> <tex-math notation="LaTeX">$_{\text {S,DR}}=171$ </tex-math></inline-formula> dB, respectively.

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A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration