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This paper presents a new design methodology for broadband Doherty architecture using the three-port input and output networks technique. The proposed topology was developed to overcome the Doherty power amplifier (DPA) bandwidth limitations. The output three-port network performs the impedance matching from any load impedance to the optimum loads for both main and peaking transistors and also combines the power delivered from the two devices at any power ratio. On the other hand, the input-splitting network is proposed for matching the input impedances of the two transistors to the source impedance. The freedom in choosing the power division ratio of the input network enables us to achieve a tradeoff between efficiency and linearity. Also, it provides a way to accomplish the phase compensation using an arbitrary phase difference between the two branches of the Doherty power amplifier and thus, helps obviate the need of the highly bandwidth limiting offset lines found in the Doherty design. A two-stage broadband Doherty power amplifier is implemented using 0.25-um GaN HEMT MMIC process to validate the proposed topology. The fabricated DPA was measured under both continuous wave (CW) and modulated signal at different operating frequencies. Across 3.3-3.7 GHz, the implemented DPA delivers a maximum output power exceeding 42 dBm, power added efficiency (PAE) over 52 % at the peak power and over 38 % in the back-off state over the operating 400 MHz bandwidth. The fully integrated circuit has a chip-size of 4.4 mm &#x00D7; 3.5 mm.

Systematic Design Methodology of Broadband Doherty Amplifier Using Unified Matching/Combining Networks With an Application to GaN MMIC Design