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A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper. The proposed approximation technique enhances the conversion speed and relieves the power hungry reference voltage buffer. The sub-radix-2 approximation only adjusts the weights of original binary DAC array without introducing additional unit capacitors and leading to reduced silicon area and power consumption. An adder based backend encoding circuit is proposed, with negligible power and silicon area overhead. Furthermore, the non-ideal DNL/INL, which are caused by incomplete DAC settling, are characterized and analysed in this paper. The peak DNL/INL values are symmetrically located at 1/4 and 3/4 of full scale. With the presence of sub-radix-2 approximation, the peak INL/DNL could be significantly reduced. The simulation results show the better performance of sub-radix-2 approximation than binary approximation. Designed in CMOS 40nm technology, it could keep a higher (>9.5-bit) effective number of bits (ENOB) with short settling time of DAC buffer, and boost the sampling rate equivalently.

A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs