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Excess source and drain (S/D) recess depth (TSD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (Ioff, Ion) in three-stacked NS channels and parasitic bottom transistor (trpbt), gate capacitance (Cgg), intrinsic switching delay time (&#x03C4;d), and static power dissipation (Pstatic) are investigated quantitatively according to the TSD variations. More S/D dopants diffuse into the trpbt with the deeper TSD, so the Ioff and Ion increase due to raised current flowing through the trpbt. Especially, the Ioff of PFETs remarkably increases above the certain TSD (TSD,critical) compared to NFETs. Furthermore, the Ion contribution of each channels having the TSD,critical is the largest at the top NS channel and the trpbt has the ignorable Ion contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) Ion contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The Cgg also increases with the deeper TSD by increasing parasitic capacitance, but fortunately, the &#x03C4;d decreases simultaneously due to the larger increasing rate of the Ion than that of the Cgg for all SoC applications. However, the Pstatic enormously increases with the deeper TSD, and low power application is the most sensitive to the TSD variations among the SoC applications. Comprehensive analysis of the inevitable trpbt effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application