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One of the main bottlenecks in the pursuit of a large-scale--chip-basedquantum computer is the large number of control signals needed to operate qubitsystems. As system sizes scale up, the number of terminals required to connectto off-chip control electronics quickly becomes unmanageable. Here, we discussa quantum-dot spin-qubit architecture that integrates on-chip controlelectronics, allowing for a significant reduction in the number of signalconnections at the chip boundary. By arranging the qubits in a two-dimensional(2D) array with $\sim$12 $\mu$m pitch, we create space to implement locallyintegrated sample-and-hold circuits. This allows to offset the inhomogeneitiesin the potential landscape across the array and to globally share the majorityof the control signals for qubit operations. We make use of advanced circuitmodeling software to go beyond conceptual drawings of the component layout, toassess the feasibility of the scheme through a concrete floor plan, includingestimates of footprints for quantum and classical electronics, as well asrouting of signal lines across the chip using different interconnect layers. Wemake use of local demultiplexing circuits to achieve an efficientsignal-connection scaling leading to a Rent's exponent as low as $p = 0.43$.Furthermore, we use available data from state-of-the-art spin qubit andmicroelectronics technology development, as well as circuit models andsimulations, to estimate the operation frequencies and power consumption of amillion-qubit processor. This work presents a novel and complementary approachto previously proposed architectures, focusing on a feasible scheme tointegrating quantum and classical hardware, and significantly closing the gaptowards a fully CMOS-compatible quantum computer implementation.

Spiderweb array: A sparse spin-qubit array