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The negative capacitance (NC) stabilization of a ferroelectric (FE) materialcan potentially provide an alternative way to further reduce the powerconsumption in ultra-scaled devices and thus has been of great interest intechnology and science in the past decade. In this article, we present aphysical picture for a better understanding of the hysteresis-free charge boosteffect observed experimentally in metal-ferroelectric-insulator-metal (MFIM)capacitors. By introducing the dielectric (DE) leakage and interfacial trappedcharges, our simulations of the hysteresis loops are in a strong agreement withthe experimental measurements, suggesting the existence of an interfacial oxidelayer at the FE-metal interface in metal-ferroelectric-metal (MFM) capacitors.Based on the pulse switching measurements, we find that the charge enhancementand hysteresis are dominated by the FE domain viscosity and DE leakage,respectively. Our simulation results show that the underlying mechanisms forthe observed hysteresis-free charge enhancement in MFIM may be physicallydifferent from the alleged NC stabilization and capacitance matching. Moreover,the link between Merz's law and the phenomenological kinetic coefficient isdiscussed, and the possible cause of the residual charges observed after pulseswitching is explained by the trapped charge dynamics at the FE-DE interface.The physical interpretation presented in this work can provide importantinsights into the NC effect in MFIM capacitors and future studies of low-powerlogic devices.

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Physical Mechanism behind the Hysteresis-free Negative Capacitance  Effect in Metal-Ferroelectric-Insulator-Metal Capacitors with Dielectric  Leakage and Interfacial Trapped Charges