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The foreseen Phase 2 pixel upgrades at the LHC have very challengingrequirements for the design of hybrid pixel readout chips. A versatile pixelsimulation platform is as an essential development tool for the design,verification and optimization of both the system architecture and the pixelchip building blocks (Intellectual Properties, IPs). This work is focused onthe implemented simulation and verification environment named VEPIX53, builtusing the SystemVerilog language and the Universal Verification Methodology(UVM) class library in the framework of the RD53 Collaboration. The environmentsupports pixel chips at different levels of description: its reusablecomponents feature the generation of different classes of parameterized inputhits to the pixel matrix, monitoring of pixel chip inputs and outputs,conformity checks between predicted and actual outputs and collection ofstatistics on system performance. The environment has been tested performing astudy of shared architectures of the trigger latency buffering section of pixelchips. A fully shared architecture and a distributed one have been described atbehavioral level and simulated; the resulting memory occupancy statistics andhit loss rates have subsequently been compared.

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips