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The Insertable B-layer (IBL) is a fourth pixel layer that will be addedinside the existing ATLAS pixel detector during the long LHC shutdown of 2013and 2014. The new four layer pixel system will ensure excellent tracking,vertexing and b-tagging performance in the high luminosity pile-up conditionsprojected for the next LHC run. The peak luminosity is expected to reach 3 x10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 andionizing dose of 250 Mrad including safety factors. The production front-endelectronics FE-I4B for the IBL has been fabricated at the end of 2011 and hasbeen extensively characterized on diced ICs as well as at the wafer level. Theproduction tests at the wafer level were performed during 2012. Selectedresults of the diced IC characterization are presented, including measurementsof the on-chip voltage regulators. The IBL powering scheme, which was chosenbased on these results, is described. Preliminary wafer to wafer distributionsas well as yield calculations are given.

Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade