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The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment.Each station of the Gigatracker needs to provide time stamping of individual particles to200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x40 pixels. The high precision time measurement of the discriminated hit signals is accomplishedwith a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approachis employed to achieve a constant time binning of 100ps. Simulation results show that an averagerms time resolution of 33ps with a power consumption of the TDC better than 33mW per columnis achieved. This contribution will present the design, simulation results and implementationchallenges of the TDC

A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)