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The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector (HPD) are presented. This detector must perform time stamping to 200 ps (RMS) or better, provide 300 μm pitch position information and operate with a dead time of 1 or less for 800 MHz-1 GHz beam rate. The demonstrator HPD Assembly comprises a readout chip with a test column of 45 pixels, alongside other test structures, bump bonded to a p-in-n detector 200μm in thickness. Validation of the performance of the HPD and the time-over-threshold timewalk compensation mechanism with both beam particles and a high precision laser system was performed and is presented. Confirmation of better than the required time stamping precision has been demonstrated and subsequent work on the design of the full-scale ASIC, dubbed TDCPix, is underway. An overview of the TDCPix architecure is given. © 2011 IOP Publishing Ltd and SISSA

Characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector