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The architecture and characterisation of the End Of Column demonstrator readoutASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof ofprinciple for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps(RMS), provide 300 mm pitch position information and operate with a dead-time of 1% or less for800MHz-1GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixelsalongside other test structures. The timewalk correction mechanism employed is measurement ofthe time-over-threshold, coupled with an off-detector look-up table. The time to digital converteris a delay locked loop with 32 contributing delay cells fed with a 320MHz to yield a nominal binsize of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisationof these assemblies has begun

Characterisation of the NA62 GigaTracker end of column readout ASIC