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An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FeI4, which requires new off-detector electronics, currently realized with two VME-based boards, which implement optical I/O functionality (BOC card) and data processing functionality (ROD card), plus a timing interface module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board

ATLAS IBL: integration of new HW/SW readout features for the additional layer of Pixel Detector