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Today, most X-ray pixel detectors used at light sources transmit raw pixeldata off the detector ASIC. With the availability of more advanced ASICtechnology nodes for scientific application, more digital functionality fromthe computing domains (e.g., compression) can be integrated directly into adetector ASIC to increase data velocity. In this paper, we describe alightweight, user-configurable detector ASIC digital architecture with on-chipcompression which can be implemented in \SI{130}{\nm} technologies in areasonable area on the ASIC periphery. In addition, we present a design toefficiently handle the variable data from the stream of parallel compressors.The architecture includes user-selectable lossy and lossless compressionblocks. The impact of lossy compression algorithms is evaluated on simulatedand experimental X-ray ptychography datasets. This architecture is a practicalapproach to increase pixel detector frame rates towards the continuous\SI{1}{\MHz} regime for not only coherent imaging techniques such asptychography, but also for other diffraction techniques at X-ray light sources.

A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging