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Demands on Field-Programmable Gate Array (FPGA) data transport have beenincreasing over the years as frame sizes and refresh rates increase. As thebandwidths requirements increase the ability to implement data transportprotocol layers using "soft" programmable logic becomes harder and start torequire harden IP blocks implementation. To reduce the number of physical linksand interconnects, it is common for data acquisition systems to requireinterleaving of streams on the same link (e.g. streaming data and streamingregister access). This paper presents a way to leverage existing FPGA harden IPblocks to achieve a robust, low latency 100 Gb/s point-to-point link withminimal programmable logic overhead geared towards the needs of dataacquisition systems with interleaved streaming requirements.

100 Gb/s High Throughput Serial Protocol (HTSP) for Data Acquisition Systems with Interleaved Streaming