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Time-digital Converter (TDC) aims to measure the arrival time of the leadingedge of the pulse signal. Our recent work presented a high resolutionmulti-phase TDC based on the Kintex-7 Field Programmable Gate Array (FPGA)device. A simple I/O tile based circular input buffer is employed to oscillatethe input signal periodically, and then a multi-phase TDC based on ISERDES corewith a 625 ps bin size is used to accomplish the multiple measurements forgetting higher resolution performance. In this paper, the design concept,architecture, as well as kernel implementation considerations are alldiscussed. To evaluate the TDC's performance, we built a verification systembased on Kintex-7 FPGA. Initial test results indicate that the TDC's effectivebin size is successfully reduced from 625 ps to 78.125 ps, and the measureddual-channel time resolution is better than 35 ps RMS.

A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA