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This paper presents the design and simulation results of a gigabittransceiver Application Specific Integrated Circuit (ASIC) called GBCR for theATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has fourupstream receiver channels and a downstream transmitter channel. Each upstreamchannel operates at 5.12 Gbps, while the downstream channel operates at 2.56Gbps. In each upstream channel, GBCR equalizes a signal received through a5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with arecovered clock, and drives an optical transmitter. In the downstream channel,GBCR receives the data from an optical receiver and drives the same type ofcable as the upstream channels. The output jitter of an upstream channel is26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps.Each upstream channel consumes 78 mW and each downstream channel consumes 27mW. Simulation results of the upstream test channel suggest that a significantjitter reduction could be achieved with minimally increased power consumptionby using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE)in addition to the linear equalization of the baseline channel. GBCR isdesigned in a 65-nm CMOS technology.

A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade