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This work presents the design of an RS(31,27) Reed Solomon encoder for a 3.2Gbps serial transmitter in 0.18 um CMOS technology. The proposed encoder isdesigned with a novel full parallel structure optimized for high speed and highstability. One data frame contains 2 interleaved RS(31,27) codes and thus itcan correct at most 20 bits of consecutive errors. A corresponding decoder isimplemented on Xilinx Kintex-7 FPGA.

Study of Full Parallel RS(31,27) Encoder for a 3.2 Gbps Serial Transmitter in 0.18 um CMOS Technology