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In the upgrade of ATLAS experiment, the front-end electronics components aresubjected to a large radiation background. Meanwhile high speed optical linksare required for the data transmission between the on-detector and off-detectorelectronics. The GBT architecture and the Versatile Link (VL) project aredesigned by CERN to support the 4.8 Gbps line rate bidirectional high-speeddata transmission which is called GBT link. In the ATLAS upgrade, besides thelink with on-detector, the GBT link is also used between different off-detectorsystems. The GBTX ASIC is designed for the on-detector front-end,correspondingly for the off-detector electronics, the GBT architecture isimplemented in Field Programmable Gate Arrays (FPGA). CERN launches theGBT-FPGA project to provide examples in different types of FPGA. In the ATLASupgrade framework, the Front-End LInk eXchange (FELIX) system is used tointerface the front-end electronics of several ATLAS subsystems. The GBT linkis used between them, to transfer the detector data and the timing, trigger,control and monitoring information. The trigger signal distributed in thedown-link from FELIX to the front-end requires a fixed and low latency. In thispaper, several optimizations on the GBT-FPGA IP core are introduced, to achievea lower fixed latency. For FELIX, a common firmware will be used to interfacedifferent front-ends with support of both GBT modes: the forward errorcorrection mode and the wide mode. The modified GBT-FPGA core has the abilityto switch between the GBT modes without FPGA reprogramming. The system clockdistribution of the multi-channel FELIX firmware is also discussed in thispaper.

Optimization on fixed low latency implementation of GBT protocol in FPGA