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The increase of the leakage current of NMOS transistors during exposure toionizing radiation is known and well studied. Radiation hardness by designtechniques have been developed to mitigate this effect and have beensuccessfully used. More recent developments in smaller feature sizetechnologies do not make use of these techniques due to their drawbacks interms of logic density and requirement of dedicated libraries. During operationthe resulting increase of the supply current is a serious challenge and needsto be considered during the system design.  A simple parametrization of the leakage current of NMOS transistors as afunction of total ionizing dose is presented. The parametrization uses atransistor transfer characteristics of the parasitic transistor along theshallow trench isolation to describe the leakage current of the nominaltransistor. Together with a parametrization of the number of positive chargestrapped in the silicon dioxide and number of activated interface traps in thesilicon to silicon dioxide interface the leakage current as a function of theexposure time to ionizing radiation results. This function is fitted to data ofthe leakage current of single transistors as well as to data of the supplycurrent of full ASICs.

Parametrization of the radiation induced leakage current increase of NMOS transistors