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We present the design and performance of a prototype ASIC digitizer forintegrated wire chamber readout, implemented in 65 nm commercial CMOStechnology. Each channel of the 4-channel prototype is composed of two 16-bitTime-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC),a front-end preamplifier and shaper, plus digital and analog buffers thatsupport a variety of digitization chains. The prototype has a multiplexeddigital backend that executes a state machine, distributes control and timingsignals, and buffers data for serial output. Laboratory bench tests measure theabsolute TDC resolution between 74 ps and 480 ps, growing with the absolutedelay, and a relative time resolution of 19 ps. Resolution outliers due tocross-talk between clock signals and supply or reference voltages are seen.After calibration, the ADC displays good linearity and noise performance, withan effective number of bits of 6.9. Under normal operating conditions thecircuit consumes 32 mW per channel. Potential design improvements to addressthe resolution drift and tails are discussed.

Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology