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In this paper we present the impact of classical electronics constraints on asolid-state quantum dot logical qubit architecture. Constraints due to routingdensity, bandwidth allocation, signal timing, and thermally aware placement ofclassical supporting electronics significantly affect the quantum errorcorrection circuit's error rate. We analyze one level of a quantum errorcorrection circuit using nine data qubits in a Bacon-Shor code configured as aquantum memory. A hypothetical silicon double quantum dot quantum bit (qubit)is used as the fundamental element. A pessimistic estimate of the errorprobability of the quantum circuit is calculated using the total number ofgates and idle time using a provably optimal schedule for the circuitoperations obtained with an integer program methodology. The micro-architectureanalysis provides insight about the different ways the electronics impact thecircuit performance (e.g., extra idle time in the schedule), which cansignificantly limit the ultimate performance of any quantum circuit andtherefore is a critical foundation for any future larger scale architectureanalysis.

Implications of Electronics Constraints for Solid-State Quantum Error Correction and Quantum Circuit Failure Probability