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Studying the electrical and structural properties of the interface of thegate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, withimportant implications for understanding and optimizing the performances ofmetal-oxide-semiconductor field effect transistor (MOSFETs). In this paper,near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigatedcombining transient gate capacitance measurements (C-t) and state of the artscanning transmission electron microscopy in electron energy loss spectroscopy(STEM-EELS) with sub-nm resolution. The C-t measurements as a function oftemperature indicated that the effective NIOTs discharge time is temperatureindependent and electrons from NIOTs are emitted toward the semiconductorvia-tunnelling. The NIOTs discharge time was modelled taking into account alsothe interface state density in a tunnelling relaxation model and it allowed tolocate traps within a tunnelling distance up to 1.3nm from the SiO2/4H-SiCinterface. On the other hand, sub-nm resolution STEM-EELS revealed the presenceof a Non-Abrupt (NA) SiO2/4H-SiC interface. The NA interface shows there-arrangement of the carbon atoms in a sub-stoichiometric SiOx matrix. A mixedsp2/sp3 carbon hybridization in the NA interface region suggests that theinterfacial carbon atoms have lost their tetrahedral SiC coordination.

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis