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Silicon nanowires present outstanding properties for electronics, energy, and environmental monitoring applications. However, their integration into microelectromechanical systems (MEMS) is a major issue so far due to low compatibility with mainstream technology, which complicates patterning and controlled morphology. This work addresses the growth of 〈111〉 aligned silicon nanowire arrays fully integrated into standard MEMS processing by means of the chemical vapor deposition-vapor liquid solid method (CVD-VLS) using silane as a precursor. A reinterpretation of the galvanic displacement method is presented for selectively depositing gold nanoparticles of controlled size and shape. Moreover, a comprehensive analysis of the effects of synthesis temperature and pressure on the growth rate and alignment of nanowires is presented for the most common silicon precursor, i.e., silane. Compared with previously reported protocols, the redefined galvanic displacement together with a silane-based CVD-VLS growth methodology provides a more standard and low-temperature (&lt;650 °C) synthesis scheme and a compatible route to reliably grow Si nanowires in MEMS for advanced applications.

Towards a full integration of vertically aligned silicon nanowires in MEMS using silane as a precursor