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We report the first experimental demonstration of recently proposedenergy-efficient single flux quantum logic, eSFQ. This logic can represent thenext generation of RSFQ logic eliminating dominant static power dissipationassociated with a dc bias current distribution and providing over two orders ofmagnitude efficiency improvement over conventional RSFQ logic. We furtherdemonstrate that the introduction of passive phase shifters allows thereduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bitoperation. Two types of demonstration eSFQ circuits, shift registers anddemultiplexers (deserializers), were implemented using the standard HYPRES 4.5kA/cm2 fabrication process. In this paper, we present eSFQ circuit design anddemonstrate the viability and performance metrics of eSFQ circuits throughsimulations and experimental testing.

Implementation of Energy Efficient Single Flux Quantum (eSFQ) Digital Circuits with sub-aJ/bit Operation