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Micro-Raman spectroscopy was employed to study the near-surface stressdistributions and origins in Si around through silicon vias (TSVs) at both roomtemperature and elevated temperatures for Cu-filled and CNT-filled TSV samples.From the observations, we proved that the stresses near TSVs are mainly fromtwo sources: 1) pre-existing stress before via filling, and 2) coefficients ofthermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress isshown to dominate the compressive regime of the near-surface stressdistribution around Cu-filled TSV structures, while pre-existing stressdominates the full range of the stress distribution in the CNT-filled TSVstructures. Once the pre-existing stress is minimized, the total stress aroundCNT-filled TSVs can be minimized accordingly. Therefore, compared to Cu-filledTSVs, CNT-filled TSVs hold the potential to circumvent the hassle ofstress-aware circuit layout and to solve the stress-related reliability issues.

On the Origins of Near-Surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias