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By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock’s opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip’s functionality and jitter measurement at the maximum frequency of 200 MHz.

A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process