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Physical un-clonable functions (PUF) play important role in hardware security due to its random response generation. It offers a wide range of security applications, such as key generation, digital rights management, and Field Programmable Gate Array (FPGA) intellectual property (IP) protection. In literature, several PUF structures of both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are used to improve the performance parameter, mainly reliability and uniqueness. Because of the large number of challenges and responses pairs (CRPS), Arbiter PUF (APUF) is widely used but suffers from less reliability and uniqueness. The proposed PUF structure is designed to achieve the ideal value of performance metrics and also to reduce the prediction rate. This paper presents a new approach to design Double Feed-Forward XOR Arbiter PUF (DFFX APUF), is a combination of Feed-Forward Arbiter PUF, the output of this combination is XORed to generate the single response. Newly proposed PUF is implemented on Xilinx Virtex-6 FPGA. The reliability and uniqueness are the parameters to evaluate the performance of the DFFX APUF and is compared with the Feed-Froward APUF and Double-APUF. The proposed PUF architecture results, the uniqueness of 5% and reliability of 8% greater than FF-APUF and Double-APUF.

Design and Implementation of Enhanced PUF Architecture onFPGA