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In this paper, a high-speed parallel residue-to-binary converter is proposed for a recently introduced moduli set  Sk={2m−1,220m+1,221m+1,…,22km+1} for a general value of k. The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases of  k=0 and k=1 are derived from the general architecture and compared with those existing in the literature. The converter for S0 is twice as fast requiring only one-half of the hardware, while that of S1 is three times as fast, but requiring only 60% of the hardware, as compared to the corresponding ones existing in the literature. Furthermore, the proposed converters are implemented using 0.5-micron CMOS VLSI technology. Based on S0 , the layouts for 8-bit, 16-bit, 32-bit and 64-bit converters are generated, and the corresponding simulation results obtained

vlsi design

A Parallel Residue-to-binary Converter for the Moduli Set <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="E1"><mml:mrow><mml:mrow><mml:mo>{</mml:mo><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mi>m</mml:mi></mml:msup><mml:mo>−</mml:mo><mml:mn>1</mml:mn><mml:mo>,</mml:mo><mml:msup><mml:mn>2</mml:mn><mml:mrow><mml:msup><mml:mn>2</mml:mn><mml:mn>0</mml:mn></mml:msup><mml:mi>m</mml:mi></mml:mrow></mml:msup><mml:mo>+</mml:mo><mml:mn>1</mml:mn><mml:mo>,</mml:mo><mml:msup><mml:mn>2</mml:mn…

A Parallel Residue-to-binary Converter for the Moduli Set {2m−1,220m+1,2