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In the emerging nanotechnology, a finest potential alternative to transistor-based technology is Quantum-dot cellular automata (QCA). It promises higher device density and lower power consumption. The predominant application of QCA is the realization of configurable blocks in the digital systems. This paper presents a new serial scan register and a boundary scan cell, essential components used for chip-level and system-level testing. The proposed majority logic gate-based 1-bit clocked D-flip-flop (DFF) and the rotating multiplexer is used in these techniques. In the first attempt, the clocked DFF is further extended to implement the 2-bit, 4-bit, serial shift register and scan flip-flop. The detailed structural and performance analysis in different aspects proves that the proposed circuits offer elevated performance in contrast to earlier reported works. The various circuit comparison factors that are to be considered in QCA are the circuit complexity, area, delay in terms of the number of clocks, and energy dissipation. Significant improvements have been enhanced in the proposed layouts as compared to traditional approaches. In addition, power dissipation analysis of the stated DFF would be carried out at 2 K Temperature using different tunnelling energy levels (0.5, 1.0, and 1.5 Ek). All the simulations are performed using QCA Designer Ver. 2.0.3 and the power analysis is performed by QCA Pro tool Ver. 1.0.

Quantum Dot Cellular Automata-Based Scan Flip-Flop and Boundary Scan Register