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This paper analyses the effect of temperature variations on the device performance of a ground plane junctionless tunnel field effect transistor (GP-JLTFET) with a high-K gate stack. Ground plane screens the electric field at the drain interface, which results in a higher effective channel length. This leads to highly suppressed ambipolarity and enhancement of the drive current. The junctionless device structure reduces the complexity of high-temperature doping processes as well. As high-gate oxide and metal gate are incorporated, this also aids in increasing the gate controllability and reduced leakage. As the tunnelling mechanism is temperature-dependent, hence, for investigating the feasibility of device application at elevated temperature, these temperature variation effects need to be analysed in depth. The primary goal of this investigation is to analyse the device dc performance parameters like drain current characteristics and subthreshold slope (SS), threshold voltage (),andratio. Furthermore, the impact of temperature on analogue/RF figures of merit has also been analysed in detail here.

DC/RF performance and temperature sensitivity of ground-plane based JLTFET