English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

This investigation demonstrates a 10-bit SAR-ADC with low power dissipation per conversion step at 50 MS/s sampling rate. The proposed ADC is featured with the split-capacitance array by using unity-gain amplifiers and designed for fibre optic gyroscope (FOG) systems. The buffers based on the unity-gain amplifiers replace the bridge capacitors of the split-capacitance array in conventional SAR ADCs to resist process variation and enhance linearity of the capacitor-array. Aside from those, improvements in time response, that is, settling time, and capacitor size have also been proved. The design was implemented using a typical 40-nm CMOS process. The INL (integral non-linearity) and the DNL (differential non-linearity) were found to be 0.56 LSB and 0.51 LSB, respectively. The SNDR and SFDR are 51.23 dB and 61.46 dB, respectively, at an input of 12.5 MHz showing ENOB to be 9.79 bits at a sampling rate of 50 MS/s.

A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems