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The demand for cost, power and area-efficient de-noising filter is increasing day by day, because of its remarkable performance in various image processing applications. In this paper, a variable-node shift-based median filter is designed for achieving low power and area utilisation. Here, the proposed design encompasses a Max Tree Extraction (MTE) unit in conjunction with various devices, like comparators, variable-node shift generators, token generators, and noise detector units, which enable low hardware requirement and minimise the power consumption. The proposed model lessens the need of complex operations, like rank generation, rank calculation and median selection. Moreover, the proposed median filter is structured by Xilinx software and the hardware implementation is done by FPGA (Virtex 7 ×C7VX980 FPGA). Additionally, the proposed model is evaluated for different test images at various noise levels. The performance of the proposed median filter design is analysed under peak signal to noise ratio (PSNR), mean square error (MSE), power, delay and area. The experimental results show that the overall performance of the proposed method is superior to the state-of-art technologies.

Low power design of energy efficient median filter