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The transistor-based CMOS technology is facing tremendous physical challenges in nano-scale design. The Quantum-dot cellular automata (QCA) have attracted the research focus as aviable alternative to CMOS technology for future designs in the nano-scale. The cell interaction property helps in information propagation in QCA. The three-input majority gate, Inverter gate are the basic building blocks. The fabrication complexity can be optimised with coplanar and clock-based wire crossing techniques. Due to its low power feature, QCA has been experiencing significant power dissipation in its wire crossing and logic-driving cell, which needs special care. Moreover, various challenges to logic synthesis are associated with design automation and integration. Underlying metal wire crossing is another concern in the implementation of a regular clocking circuit. Extensive design proposals in QCA have been studied bypassing regular clocking and ends up with a question of proper fabrication or buildability. This research proposes an emerging technique to develop an efficient, scalable regular clocking scheme incorporating minimal metal wire crossing. The proposed clocking is employed for the cost-effective and power-efficient circuit design in both the sequential and the combinational approach. QCADesigner is used for circuit synthesis, whereas QCAPro and QCADesignerE have been utilised for energy dissipation analysis.

Regular Clocking based Emerging Technique in QCA Targeting Low Power Nano Circuit