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Stability and performance of conventional SRAM cells operating at low voltages are severely affected due to enhanced process variations. This paper proposes a Transmission Gate (TG) based 9 T SRAM cell with independent read/write operation and compares its performance with 6 T, 8 T and 10 T SRAM cells. The enhanced read and write ability of the cell is due to the selective use of positive feedback loop. To show the efficacy of the proposed technique, simulations are carried out using 130 nm UMC technology files on Cadence Virtuoso and HSPICE. The transistor size with minimum length and width is used in each configuration using the UMC 130 nm technology file for all the simulations. Various body biasing techniques (Reverse Body Bias and Forward Body Bias) are applied to reduce active and standby power. It has been observed that the proposed cell shows better results in terms of enhanced read, write and hold stability and for reduced power also. Further, the write access time is less for the proposed cell. The layout of the proposed architecture is also shown.

Robust low power transmission gate (TG) based 9T SRAM cell with isolated read and write operation