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3D ICs, a novel technology, might significantly impact multicore NoCs with hundreds or thousands of processing components on a single chip. Multiple 2D chips can be stacked vertically to create multiple active processing elements at various levels. Adding active device layers to 3D ICs can enhance system performance, increase functionality, and increase packing density. New architectural and IC technology advancements hinder energy-efficient design research. Achieving a balance between chip power and performance is crucial. This paper describes the “Dynamic Low Power Management Method in 3DWiNoC” (DLPM 3DWiNoC) architecture, which enables self-organized, centrally managed service management using Smart Master Agents. The approach utilizes SMA's ODA DD module for self-organized, centrally managed service management. To improve power regulation, data flow across vertical interconnects (TSVs) is reconfigured based on a dynamic evaluation of channel link use. SMA aims to reduce congestion by increasing connection utilization through high-frequency, bi-directional vertical channels via TSVs. The suggested system is modeled in MATLAB Simulink. Compared to 3D stacking, TSV stacking of vertical interconnects with the SMA method ensures low parasitic (latency and power) and higher bandwidth with higher vertical wire densities. Experimental results show that the proposed architecture decreases area overhead by 5%-7%, network latency by 12%-15%, and NoC power consumption by 15%-20% compared to the present multi-NoC design.

Dynamic low power management technique for decision directed inter-layer communication in three dimensional wireless network on chip