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We have measured the low-frequency time instability known as charge offsetdrift of Si/SiO$_2$ single electron devices (SEDs) with and without an overallpoly-Si top gate. We find that SEDs with a poly-Si top gate have significantlyless charge offset drift, exhibiting fewer isolated jumps and a factor of tworeduction in fluctuations about a stable mean value. The observed reduction canbe accounted for by the electrostatic reduction in the mutual capacitance $C_m$between defects and the quantum dot, and increase in the total defectcapacitance $C_d$ due to the top gate. These results depart from the acceptedunderstanding that the level of charge offset drift in SEDs is determined bythe intrinsic material properties, forcing consideration of the device designas well. We expect these results to be of importance in developing SEDs forapplications from quantum information to metrology or wherever charge noise orintegrability of devices is a challenge.

Effect of device design on charge offset drift in Si/SiO$_2$ single electron devices