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This paper presents an architecture of high-resolution delay generatorimplemented in a single field programmable gate array (FPGA) chip by exploitingthe method of utilizing dedicated carry chains. It serves as the core componentin various physical instruments. The proposed delay generator contains thecoarse delay step and the fine delay step to guarantee both large dynamic rangeand high resolution. The carry chains are organized in the Vernier delay loopstyle to fulfill the fine delay step with high precision and high linearity.The delay generator was implemented in the EP3SE110F1152I3 Stratix III devicefrom Altera on a self-designed test board. Test results show the obtainedresolution is 38.6 ps, and the differential nonlinearity (DNL) and integralnonlinearity (INL) is in the range of (-0.18 least significant bit (LSB),0.24LSB)\(-0.02 LSB,0.01 LSB) under the nominal supply voltage of 1100 mV andenvironmental temperature of 20 degrees centigrade. The delay generator is alsorather resource cost efficient which uses only 668 LUTs and 146 registers intotal.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA