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The integration of III-V on silicon is still a hot topic as it will open up away to co-integrate Si CMOS logic with photonic vices. To reach this aim,several hurdles should be solved, and more particularly the generation ofantiphase boundaries (APBs) at the III-V/Si(001) interface. Density functionaltheory (DFT) has been used to demonstrate the existence of a double-layer stepson nominal Si(001) which is formed during annealing under proper hydrogenchemical potential. This phenomenon could be explained by the formation ofdimer vacancy lines which could be responsible for the preferential andselective etching of one type of step leading to the double step surfacecreation. To check this hypothesis, different experiments have been carried inan industrial 300 mm MOCVD where the total pressure during the anneal step ofSi(001) surface has been varied. Under optimized conditions, an APBs-free GaAslayer was grown on a nominal Si(001) surface paving the way for III-Vintegration on silicon industrial platform.

Toward III-V/Si co-integration by controlling biatomic steps on hydrogenated Si(001)