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We report on gate hysteresis in resistance on high quality graphene/h-BNdevices. We observe a thermal activated hysteretic behavior in resistance as afunction of the applied gate voltage at temperatures above 375K. In order toinvestigate the origin of the hysteretic phenomenon, we design heterostructuresinvolving graphene/h-BN devices with different underlying substrates such as:SiO2/Si and graphite; where heavily doped silicon and graphite are used as aback gate electrodes, respectively. The gate hysteretic behavior of theresistance shows to be present only in devices with an h-BN/SiO2 interface andis dependent on the orientation of the applied gate electric field and sweeprate. Finally, we suggest a phenomenological model, which captures all of ourfindings based on charges trapped at the h-BN/SiO2. Certainly, such hystereticbehavior in graphene resistance represents a technological problem for theapplication of graphene devices at high temperatures, but conversely, it canopen new routes for applications on digital electronics and graphene memorydevices.

Thermo Activated Hysteresis on High Quality Graphene/h-BN Devices