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The basic reason for enhanced electron capture time, τc , of the oxide single trap dependence on drain current in the linear operation regime of p+-p-p+ silicon field effect transistors (FETs) was established, using a quantum-mechanical approach. A strong increase of τc slope dependence on channel current is explained using quantization and tunneling concepts in terms of strong field dependence of the oxide layer single trap effective cross-section, which can be described by an amplification factor. Physical interpretation of this parameter deals with the amplification of the electron cross-section determined by both decreasing the critical field influence as a result of the minority carrier depletion and the potential barrier growth for electron capture. For the NW channel of n+-p-n+ FETs, the experimentally observed slope of τc equals (−1). On the contrary, for the case of p+-p-p+ Si FETs in the accumulation regime, the experimentally observed slope of τc equals (−2.8). It can be achieved when the amplification factor is about 12. Extraordinary high capture time slope values versus current are explained by the effective capture cross-section growth with decreasing electron concentration close to the nanowire-oxide interface

Single trap in liquid gated nanowire FETs: Capture time behavior as a function of current