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Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown (TDDB) tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors (MOSFET). This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise (RTN) fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase of the leakage current towards the compliance, culminating in a thermal runaway and hard breakdown (HBD). The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16Ǻ) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo (KMC) defect generation and multi-phonon trap assisted tunneling (PTAT) models. We show that the transition from the digital to the analog regime is governed by a critical voltage (VCRIT), which determines the reliability margin in the post breakdown phase. Our results have a significant impact on the post-breakdown operational reliability of SiON and advanced high-κ – SiOx interfacial layer (HK-IL) gate stacks, wherein the SiOx layer seems to be the weakest link for percolation event

Resilience of ultra-thin oxynitride films to percolative wear-out and reliability implications for high-κ stacks at low voltage stress