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Channel conductance measurements can be used as a tool to study thermallyactivated electron transport in the sub-threshold region of state-of-artFinFETs. Together with theoretical Tight-Binding (TB) calculations, thistechnique can be used to understand the evolution of source-to-channel barrierheight (Eb) and of active channel area (S) with gate bias (Vgs). Thequantitative difference between experimental and theoretical values that weobserve can be attributed to the interface traps present in these FinFETs.Therefore, based on the difference between measured and calculated values of(i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods ofinterface trap density (Dit) metrology are outlined. These two methods areshown to be very consistent and reliable, thereby opening new ways of analyzingin situ state-of-the-art multi-gate FETs down to the few nm width limit.Furthermore, theoretical investigation of the spatial current density revealvolume inversion in thinner FinFETs near the threshold voltage.

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs