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This paper describes a new technique for minimising power dis- sipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spu- rious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. This paper presents a new algorithm which determines the primary input change time such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application. Exhaustive experimental results using compact and non compact test sets demonstrate substan- tial savings in power dissipation using a simulated annealing-based design space exploration. As an example saving of 34% in power dissipation for benchmark circuit s713 is achieved.

Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing